Many applications performed on microprocessors or digital signal processors require the generation of addresses to fetch data from memory. One such application requires the appearance of a circular buffer such that data stored in a contiguous, finite portion of a memory array appears to be endless. The addressing technique used for circular buffers, known as modulo addressing, provides that an address stored in an address pointer will be incremented or decremented by a predetermined displacement for each memory access until a beginning or ending address boundary is reached or exceeded. When a beginning or ending address boundary is reached or exceeded, the address pointer for the next memory access will "wrap around" to the other end of the address range of the finite array.
Software addressing techniques have typically been used to generate modulo addresses in microprocessors. While only a few instruction cycles are required for each modulo address generating operation, in applications requiring intensive modulo address generation, as are often incurred in digital signal processing, a detrimental impact on processor performance occurs. Implementation of modulo addressing in hardware can obviate the detrimental impact on processor performance.
Modulo addressing is achieved in an address arithmetic unit by associating with a memory pointer a first register which stores either a beginning address or an ending address, and a second register which stores either the other of the ending or beginning address, or the length of the circular buffer being defined. As an example of modulo addressing, the first register may be set with a beginning address and the second register may be set with an ending address to define the address range of the finite array that comprises the circular buffer.
Known modulo addressing techniques are described in U.S. Pat. Nos. 5,623,621, 4,908,748, and 4,800,524. One shortcoming of existing modulo addressing techniques is that they are either complex and slow, or are not true modulo addressing techniques. Present modulo addressing techniques either restrict the increment or decrement displacement value to be one or restrict the size of the number of locations of the circular buffer relative to the displacement value such that the number of locations of the circular buffer is an integral multiple of the displacement value. This limitation is to assure that when memory locations in the circular buffer are addressed, and the address pointer is post incremented or post decremented in preparation for accessing a subsequent address in the circular buffer, the beginning address or ending address will not be bypassed or skipped-over. Restricting the increment or decrement displacement value to be one, assures that eventually the address pointer will take on the beginning address or the ending address generated as a result of the post increment or post decrement operation, and that a comparison to the address stored in the beginning address register or ending address register will result in a match that will cause the address generator to "wrap around" to the other end of the array.
What is needed is a true modulo addressing technique that accommodates any displacement value, buffer size and location, while using simple hardware that does not limit the speed of operation of a digital signal processor employing the technique.